1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, e.g., a NAND electrically erasable and programmable ROM (EEPROM) having a control gate and floating gate and including a memory cell for storing multilevel data having two or more values.
2. Description of the Related Art
In a write operation of a NAND EEPROM, a verification operation (read operation) for verifying whether data is written in a memory cell is performed after a programming operation. When writing only binary data in a memory cell, only one read operation is necessary for one programming operation. However, three read operations are necessary when writing quaternary data in a memory cell, and seven read operations are necessary when writing octernary data in a memory cell. That is, read operations corresponding to each level are necessary, and this prolongs the write time.
Note that as prior art relevant to the present invention, a nonvolatile semiconductor memory has been proposed which comprises a write circuit which writes data in a memory cell by supplying a write voltage Vpgm and write control voltage VBL to the memory cell, writes data in the memory cell by changing the value of the write control voltage VBL when the memory cell has reached a first written state, and inhibits write to the memory cell by changing the value of the write control voltage VBL to Vdd when the memory cell has reached a second written state (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2003-196988).